1. Field of the Invention
The present invention relates to a battery back-up apparatus for maintaining data in a posted write cache in the event of a primary power failure and a method for determining if live data is present in the posted write cache upon power-up.
2. Description of the Related Art
The performance of the microprocessor or central processing unit (CPU) of a computer system has increased dramatically due to the expanding personal computer and small work station computer markets. For example, microprocessors have gone from 8 bit data widths and operating frequencies of 1 MHz to 32 bit data widths and basic clock rates of 33 MHz. The internal electronic memory of computer systems, typically implemented by dynamic and static random access memory (RAMs), has basically kept pace with the advancing CPU technology so that a computer system's main memory implemented by RAM is faster and more reliable. In contrast, the mass data storage portion of a computer system has experienced only modest growth in speed and reliability. This trend is undesirable since the overall system speed is not increased substantially in systems where input/output (I/O) operations are emphasized. In many applications, for example, a substantial number of reads and writes to the mass data storage devices or hard disk drive media essentially becomes a bottleneck of the computer system.
In the past few years, a new trend in mass data storage systems, generally referred to as disk array systems, has emerged for improving transfer performance. A disk array system comprises a multiple number of smaller disk drives organized into an array of drives accessed as a single logical unit. The disk array system replaces a single large expensive data drive to achieve a high capacity data storage system with a very high data transfer rate. A technique referred to a "striping" further enhances the effective transfer rate, especially if large amounts of data are frequently transferred to and from the disk array system. The primary problem with disk array systems is that several smaller disk drives ganged together dramatically decreases the mean time that any one disk will fail, which, in turn, increases the risk of data loss. The problem has been addressed by including redundancy in the disk array system so that the data lost on any failed disk drive can be reconstructed through the redundant information stored on the surrounding disk drives. Five different levels of redundant arrays of inexpensive disks (RAID) are introduced and analyzed by D. Patterson, G. Gibson and R. Katz, "A Case for Redundant Arrays of Inexpensive Disks (RAID)", December, 1987. Other relevant articles include "Some Design Issues of Disk Arrays" by Spencer Ng April, 1989 IEEE, and "Disk Array Systems" by Wes E. Meador, April, 1989 IEEE.
Many techniques have been proposed including data protection and recovery techniques which have improved the speed and reliability of disk array systems. Nonetheless, there may be disadvantages when a disk array system is combined with traditional operating systems, such as DOS (disk operating system) and UNIX, where these operating systems perform many small writes which are often smaller then the stripe size of the disk array system resulting in partial stripe write operations. Disk performance is adversely effected because redundant information must be updated on those drives containing the redundant information each time a write occurs on any of the other drives. This is especially true in the case of small writes, where updates may require two reads and two writes for every write operation to compute and write the parity sector. It becomes necessary therefore to access data from drives not being written to in order to update parity information. Thus, delays occur due to seek time and rotational latency of the disk drives as well as lost time due to additional reads which are necessary to generate the redundant data in a disk array system.
In earlier systems, the host computer itself had to perform the operation of data distribution and control of the various controller boards and the specific drives on a given controller board, as well as perform various parity operations required to generate the necessary data redundancy. This significantly tied up the host computer. Recent bus architecture developments including the use of "bus masters" can perform these functions freeing up the host computer. A bus master may take control of the computer system at certain times and transfer data between the bus master and the system memory without requiring the service of the main or host processor. The bus master can then release the bus back to the host processor when the transfers are not necessary. In this manner, coprocessing tasks can be developed. The various buses or architectures are exemplified by the Micro Channel Architecture (MCA) developed by International Business Machines Corporation (IBM) or the Extended Industry Standard Architecture (EISA). A copy of the EISA specification, provided as Appendix 1 to U.S. Pat. No. 5,101,492, which is hereby incorporated by reference, explains the requirements of an EISA system. Thus it became obvious to place a local processor on a separate board which could be inserted into these busses for disk coprocessing functions. However, it then became critical, particularly when combined with a disk array system, to allow optimal data transfer capabilities without otherwise slowing down the various devices and capabilities.
To this end, Compaq Computer Corporation developed a disk array controller with improved parity development. The disk array controller was incorporated in a product referred to as the Intelligent Drive Array or IDA, which was sold in December, 1989 and thereafter. The system operated as a bus master in a personal computer. A local processor was included to handle and control operations in the disk array controller, and was interfaced with a bus master controller and with a data transfer controller. The data transfer controller also interfaced with the bus master controller. The bus master controller was used to provide disk array system access to the host computer system for transferring disk commands and data. The transfer controller operated as a direct memory access (DMA) controller having four main channels.
A second avenue of obtaining and returning data and commands to the host system was through a compatibility controller. The compatibility controller was also linked to the transfer controller. Additionally, up to eight individual hard disk drives, which have integrated device controllers, were linked to the transfer controller. Finally, an amount of transfer buffer memory was coupled to the transfer controller. Eventually the need for even higher throughput then that provided by the IDA was needed was applications grew larger and local area networks (LANs) became larger, the IDA being primarily used in a file server on the LAN.
Several other techniques have been proposed and used which improve the hard disk drives themselves where the drives include intermediate buffers to temporarily contain data written to and read from the disk drive. For example, the typical drive systems of today use interface drive electronics (IDE) where the disk drives include a look ahead buffer which reads an entire extra track every time it reads a requested track. In this manner, the information on the look ahead buffer can be retrieved much quicker on the next read access. This technique has been expanded until some drives actually use multiple track look ahead buffers. There are also drives which include a buffer for write operations where data is written to the buffer in the drive before actually being written on the hard drive system so that the computer system does not have to wait for additional seek delays. Drive buffers have marginally improved the performance of the hard disk drive system but are typically limited to relatively small buffer sizes since larger buffers substantially increase the cost of each drive.
Still other techniques have been used to increase the overall speed and performance of a computer system. In one method, part of the internal RAM of a computer system is implemented to appear as a logical disk drive to the computer so that data is written to it instead of a logical disk drive. This technique eliminates delays to the disk drive during use since the data is saved much more quickly in RAM. The data must be transferred, however, to the disk array system before the computer system is turned off. Another technique is referred to as disk caching which is similar to the above technique. A portion of the computer's main memory is used instead as a disk cache which serves as an intermediary storage device for disk memory. A technique referred to as write posting writes data to the cache and indicates that the operation is complete. The write operation is completed later, when the data is written to the disk array system, at a more opportune time such as when the system is idle or less active. These techniques are unacceptable if a high percentage of the data is critical. Should a power failure occur while the critical data resides in RAM before being written to the disk array system, the data is irretrievably lost. Therefore conventional write posting to a cache is not considered acceptable in many environments, such as networks.
The techniques discussed above have improved I/O throughput, but further speed increases are now necessary due to constant demands for increasing speed and reliability. It is therefore desirable to improve the performance of a computer system by substantially reducing delays of writing data to the disk array system without substantially increasing the risk of losing critical data.